The present invention relates generally to integrated circuits, and more specifically to synchronizing an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal.
In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, data words are placed on a data bus of the memory device in synchronism with the external clock signal, and the memory device must latch these data words at the proper times to successfully capture each data word. To latch the applied data words, an internal clock signal is developed in response to the external clock signal, and is typically applied to storage circuits such as latches contained in the memory device to thereby clock the data words into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the data words. In the present description, xe2x80x9cexternalxe2x80x9d is used to refer to signals and operations outside of the memory device, and xe2x80x9cinternalxe2x80x9d to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different clock synchronization circuits have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. FIG. 1 is a functional block diagram illustrating a conventional delay-locked loop 100 including a variable delay line 102 that receives a clock buffer signal CLKBUF and generates a delayed clock signal CLKDEL in response to the clock buffer signal. The variable delay line 102 controls a variable delay VD of the CLKDEL signal relative to the CLKBUF signal in response to a delay adjustment signal DADJ. A feedback delay line 104 generates a feedback clock signal CLKFB in response to the CLKDEL signal, the feedback clock signal having a model delay D1+D2 relative to the CLKDEL signal. The D1 component of the model delay D1+D2 corresponds to a delay introduced by an input buffer 106 that generates the CLKBUF signal in response to an external clock signal CLK, while the D2 component of the model delay corresponds to a delay introduced by an output buffer 108 that generates a synchronized clock signal CLKSYNC in response to the CLKDEL signal. Although the input buffer 106 and output buffer 108 are illustrated as single components, each represents all components and the associated delays between the input and output of the delay-locked loop 100. The input buffer 106 thus represents the delay D1 of all components between an input that receives the CLK signal and the input to the variable delay line 102, and the output buffer 108 represents the delay D2 of all components between the output of the variable delay line and an output at which the CLKSYNC signal is developed.
The delay-locked loop 100 further includes a phase detector 110 that receives the CLKFB and CLKBUF signals and generates a delay control signal DCONT having a value indicating the phase difference between the CLKBUF and CLKFB signals. One implementation of a phase detector is described in U.S. Pat. No. 5,946,244 to Manning (Manning), which is assigned to the assignee of the present patent application and which is incorporated herein by reference. A delay controller 112 generates the DADJ signal in response to the DCONT signal from the phase detector 110, and applies the DADJ signal to the variable delay line 102 to adjust the variable delay VD. The phase detector 110 and delay controller 112 operate in combination to adjust the variable delay VD of the variable delay line 102 as a function of the detected phase between the CLKBUF and CLKFB signals.
In operation, the phase detector 110 detects the phase difference between the CLKBUF and CLKFB signals, and the phase detector and delay controller 112 operate in combination to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted the phase of the CLKFB signal from the feedback delay line 104 is adjusted accordingly until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop 100 has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be xe2x80x9clocked.xe2x80x9d When the delay-locked loop 100 is locked, the CLK and CLKSYNC signals are synchronized as long as the feedback delay line 104 accurately models the delays D1, D2 of the input and output buffers 106, 108, as will be discussed in more detail below. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop 100 is locked), the variable delay VD has a value of NTCKxe2x88x92(D1+D2) as indicated in FIG. 1, where N is an integer and TCK is the period of the CLK signal. When VD equals NTCKxe2x88x92(D1+D2), the total delay of the CLK signal through the input buffer 106, variable delay line 102, and output buffer 108 is D1+NTCKxe2x88x92(D1+D2)+D2, which equals NTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLK signal and the two signals are synchronized since the delay is an integer multiple of the period of the CLK signal. Referring back to the discussion of synchronous memory devices above, the CLK signal corresponds to the external clock signal and the CLKSYNC signal corresponds to the internal clock signal.
FIG. 2 is a signal timing diagram illustrating various signals generated during operation of the delay-locked loop 100 of FIG. 1. In response to a rising-edge of the CLK signal at a time T0, the CLKBUF signal goes high the delay D1 later at a time T1. Initially, the variable delay VD as a value VD1, causing the CLKDEL signal to go high at a time T3 and the CLKSYNC signal to go high at a time T4. At this point, note that the positive-edge of the CLKSYNC signal at the time T4 is not synchronized with the CLK signal, which transitions high at a time T5. In response to the rising-edge of the CLKDEL signal at the time T3, the CLKFB goes high at a time T6, which occurs before a positive-edge of the CLKBUF signal occurring at a time T7. Thus, the positive-edge of the CLKFB signal occurs at the time T6 while the positive-edge of the CLKBUF occurs at the time T7, indicating there is a phase shift between the two signals. The phase detector 110 (FIG. 1) detects this phase difference, and generates the DCONT signal just after the time T7 at a time T8 which, in turn, causes the delay controller 112 (FIG. 1) to generate the DADJ signal to adjust the value of the variable delay VD to a new value VD2 and thereby synchronize the CLK and CLKSYNC signals, as depicted at a time T9. At this point, note that the variable delay VD results in an approximately zero phase difference between the CLKBUF and CLKFB signals, as indicated at a time T10.
From this description of the conventional delay-locked loop 100, it is seen that in order for the CLK and CLKSYNC signals to be accurately synchronized, the feedback delay line 104 must accurately model the delay D1 of the input buffer 106 and delay D2 of the output buffer 108. For example, if the delay D2 of the output buffer 108 has a value D2xe2x80x2 instead of D2, the delay-locked loop 100 will be locked (i.e., phase difference between CLKBUF and CLKFB equals zero), but the CLK and CLKSYNC signals will not be synchronized, as illustrated at a time T11 in FIG. 2. In a conventional double-data rate (DDR) synchronous dynamic random access memory (SDRAM), such a situation may arise when data drivers in the memory device change from a full-drive operating mode to a reduced-drive operating mode, as will now be described in more detail. Although the principles described herein are discussed with reference to a DDR SDRAM, the principles are applicable to any memory device that may include a clock synchronization circuit for synchronizing internal and external signals, such as conventional synchronous DRAMs (SDRAMs), as well as packetized memory devices like SLDRAMs and RDRAMs, and are equally applicable to any integrated circuit that must synchronize internal and external clocking signals.
Referring back to FIG. 1, in a conventional DDR SDRAM the output buffer 108 corresponds to a data driver that receives a data signal DQ and outputs the data signal in response to being clocked by the CLKDEL signal. In this way, as long as the delay D2 of the output buffer 108 is accurately modeled by the feedback delay line 104, the output buffer outputs the DQ signal on a data bus of the DDR SDRAM in synchronism with the CLK signal. In conventional DDR SDRAMs, however, the output buffer 108 operates in either a full-drive mode or a reduced-drive mode, and the delay D2 of the output buffer can vary between modes. More specifically, in a conventional DDR SDRAM an extended load mode register includes an output drive strength bit that determines whether the output buffer 108 operates in the full-drive or reduced-drive mode of operation. A memory controller typically sets the output drive strength bit in the extended load mode register via a load mode register command to thereby place the output buffer 108 in the desired operating mode. The output buffer 108 is typically placed in the full-drive mode when the DDR SDRAM is being utilized in a conventional application, such as on a conventional memory module, while the output buffer may be placed in the reduced-drive mode when the DDR SDRAM is being utilized in a point-to-point application such as on a graphics card, as will be appreciated by those skilled in the art. During the full-drive mode, the output buffer 108 provides sufficient current to drive the DQ signals to full-range voltages for a particular loading of the data bus, while during the reduced-drive mode the buffer provides a reduced current to drive the DQ signals to reduced voltages given the same loading of the data bus, as will also be appreciated by those skilled in the art.
FIG. 3 is a signal timing diagram that illustrates the operation of the output buffer 108 in the full-drive and reduced-drive modes of operation. In the example of FIG. 3, the CLKDEL signal goes high at a time T0, which occurs the delay D2 before the CLK signal goes high at a time T1. Three signal diagrams 300-304 below the CLK and CLKDEL signals illustrate the three possible scenarios for the operation of the output buffer 108 in outputting the DQ signal when switching between the full-drive and reduced-drive mode of operation. In the first diagram 300, the output buffer 108 has substantially the same delay D2 in both the full-drive and reduced-drive modes of operation. As a result, the DQ signals in diagram 300 are output in synchronism with the CLK signal in both the modes of operation, as illustrated by the signals for both modes crossing at the time T1. In contrast, the signal diagram 302 illustrates a situation where the output buffer 108 outputs the DQ signal in synchronism with the CLK signal at the time T1 in the full-drive mode of operation, but outputs the DQ signal at a different time T2 earlier than the time T1 in the reduced-drive mode of operation. In this example, the output buffer 108 has a delay D2xe2x80x2 that is less than the delay D2 modeled by the feedback delay line 104 (FIG. 1) in the reduced-drive mode, resulting in the DQ signal being output at the earlier time T2 relative to the CLK signal at the time T1.
The signal diagram 304 illustrates the third situation where the output buffer 108 outputs the DQ signal in synchronism with the CLK signal at the time T1 in the full-drive mode of operation, but outputs the DQ signal at a different time T3 later than the time T1 in the reduced-drive mode of operation. In this situation, output offer 108 has a delay D2xe2x80x2 that is greater than the delay D2 modeled by the feedback delay line 104 in the reduced-drive mode, resulting in the DQ signal being output at the later time T3 relative to the CLK signal at the time T1. Thus, FIG. 3 illustrates that in a conventional DDR SDRAM the DQ signals placed on a data bus of the memory device may not be placed on the data bus in synchronism with the CLK signal when the output buffers 108 switch between full-drive and reduced-drive modes of operation. An access time TAC(MIN) and an access time TAC(MAX) are specified for the memory device, and correspond to the maximum time before and after, respectively, the transition of the CLK signal at the time T1 that the transition of the DQ signal can occur. A conventional memory device may not satisfy the access times TAC(MIN), TAC(MAX) in both the full- and reduced-drive modes of operation. In the example of FIG. 3, the signal diagram 302 illustrates a situation where the memory device does not satisfy the access time TAC(MIN) during the reduced-drive mode, while the signal diagram 304 illustrates a situation where the memory device does not satisfy the time TAC(MAX) during the reduced-drive mode.
There is a need for a outputting data and other signals in synchronism with an external clock signal in memory devices such as DDR SDRAMs that include output buffers that can operate in full-drive and reduced-drive modes of operation.
According to one aspect of the present invention, a delay-locked loop, includes a variable delay line that receives an input clock signal and generates a delayed clock signal responsive to the input clock signal. The delayed clock signal has a delay relative to the input clock signal and the variable delay circuit controls the value of the delay responsive to a delay control signal. A mode delay line receives an output drive strength signal and generates a mode delayed clock signal having a mode delay relative to the delayed clock signal. The mode delay is a function of the output drive strength signal. A feedback delay line generates a feedback clock signal responsive to the mode delayed clock signal. The feedback clock signal has a model delay relative to the mode delayed clock signal. A comparison circuit receives the input and feedback clock signals and generates the delay control signal in response to the relative phases of these clock signals.
According to another aspect of the present invention, a delay-locked loop includes a variable delay line adapted to receive an input clock signal and generate a delayed clock signal responsive to the input clock signal. The delayed clock signal has a delay relative to the input clock signal and the variable delay circuit controls the value of the delay responsive to a delay control signal. A comparison circuit receives the input clock signal and generates the delay control signal in response to the relative phases of the delayed and input clock signals. A mode delay line receives an output drive strength signal and generates a mode delayed clock signal having a mode delay relative to the delayed clock signal. The mode delay is a function of the output drive strength signal.